Output stages comprising push-pull arrangements are well-known in the art. A drive signal is typically provided to the input of such an output stage, the output stage generating an output signal which represents an amplified version of the drive signal. A known exemplary prior art output stage arrangement in which a transformer is used as a combiner is illustrated in FIG. 1.
As illustrated in FIG. 1, the output stage comprises a pair of transistors 12 and 14, and a phase splitter 10. A drive signal is provided on an input line 16 to the input of the phase splitter 10. The phase splitter 10 splits the drive signal on line 16 into two phases (0° and 180°), each of which is delivered on respective output lines 18 and 20 of the phase splitter 10. The respective phases of the drive signal on lines 18 and 20 are connected to the control nodes of the transistors 12 and 14 respectively. The transistors 12 and 14 in the illustrative example of FIG. 1 are FET devices, and the control nodes are therefore the gates of the FETs. The transistor 12 amplifies portions of the input waveform and its drain is connected to a supply voltage VH via a primary winding 24 of a transformer 11. The transistor 14 amplifies low voltage portions of the input waveform and its drain is connected to supply voltage VL via another primary winding 26 of the transformer 11. The source of each transistor 12 and are commonly connected to an electrical ground 22. In general, VH≠VL, and VH>VL.
A winding 13 of a secondary side of the transformer 11 is connected between electrical ground 15, and one terminal of an output load 17. The other terminal of the output load 17 is connected to electrical ground at node 19.
In FIG. 2 there is illustrated an example asymmetric waveform plot of voltage against time which voltage may typically form the drive signal DRIVE on line 16. As illustrated in FIG. 2, the drive signal denoted by reference numeral 28 is asymmetrical with respect to a DC slice voltage VSLICE denoted by horizontal line 30. The slice voltage VSLICE represents the cross-over point or slicing point between the two halves of the output stage comprising the transistors 12 and 14 in processing such a drive signal in prior art arrangements. In general, the portions of the drive signal above the slicing voltage VSLICE as denoted by line 30 are handled by the high-side transistor 12, and the portions of the drive signal below the slicing voltage VSLICE 30 are handled by the low-side transistor 14. Thus one half of the output stage amplifies the signal above the crossing point 30, and the other half of the output stage amplifies the signal below the crossing point 30.
Illustrated in FIG. 3 is a plot of dissipated power against slicing voltage for the two transistors 12 and 14 of the output stage in the prior art arrangement of FIG. 1. The plotted curve 32 denotes the power dissipated in the transistor 12, denoted PA. The plotted curve 34 denotes the power dissipated in the transistor 14, denoted PB. The plotted dashed line 36 denotes the total power dissipated in the output stage comprising the transistors 12 and 14 in combination. In an ideal scenario, the crossing point or slicing point is determined to minimise the total power dissipated by the transistors 12 and 14. This occurs when the power dissipated in transistors 12 and 14 is equal. Thus as illustrated in FIG. 3, in the ideal scenario the crossing point is defined by a slicing voltage VSLICE_MIN, denoted by a horizontal line 40 which passes through the intersection of the plots 32 and 34. This represents the point at which half of the power in the output stage is handled by the transistor 12, and half of the power in the output stage is handled by the transistor 14.
It should be noted that in the above description there is discussed dissipation of power in the transistors 12 and 14. Power may also be dissipated—at least in part—in the transformer which forms part of the output stage. As the transformer is an example of a combiner stage, in general the power dissipated in the output stage is sum of the power dissipated in the drive transistors and power dissipated in the combiner.
The object of the invention is to maximise the efficiency of an output stage for any waveform statistics.